diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 01:03:33 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 01:03:33 -0800 |
| commit | f6c0ec1d09c9bc065cc7266b299b41ebb59d6e26 (patch) | |
| tree | c86d01623e4ac9ebeb91e61441812ddccc20fa07 /techlibs/xilinx/cells_sim.v | |
| parent | 4ba6f4f0d7c5754e04a0347a2b43a8640f7a6a35 (diff) | |
| parent | 5e67df38edf5207a9b816946b094448cd6a52f88 (diff) | |
| download | yosys-f6c0ec1d09c9bc065cc7266b299b41ebb59d6e26.tar.gz yosys-f6c0ec1d09c9bc065cc7266b299b41ebb59d6e26.tar.bz2 yosys-f6c0ec1d09c9bc065cc7266b299b41ebb59d6e26.zip | |
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index d863b2ad7..d845b324f 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -59,6 +59,34 @@ module OBUF( assign O = I; endmodule +module IOBUF ( + (* iopad_external_pin *) + inout IO, + output O, + input I, + input T +); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + assign IO = T ? 1'bz : I; + assign O = IO; +endmodule + +module OBUFT ( + (* iopad_external_pin *) + output O, + input I, + input T +); + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + assign O = T ? 1'bz : I; +endmodule + module BUFG( (* clkbuf_driver *) output O, |