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| author | Benedikt Tutzer <benedikt.tutzer@gmail.com> | 2019-10-15 10:13:21 +0200 |
|---|---|---|
| committer | Benedikt Tutzer <benedikt.tutzer@gmail.com> | 2019-10-15 10:13:21 +0200 |
| commit | f8f572fbfc4e5de3afa7dc05f5fa1feff87aabd3 (patch) | |
| tree | daca10f9ee8149bc7ee13eb9cf89702886275947 /techlibs/xilinx/cells_sim.v | |
| parent | 79be986e2248540854c3e8e1e21f5bf971079690 (diff) | |
| parent | 2daa56859f51631992cc172ccddad55e741b0c3d (diff) | |
| download | yosys-f8f572fbfc4e5de3afa7dc05f5fa1feff87aabd3.tar.gz yosys-f8f572fbfc4e5de3afa7dc05f5fa1feff87aabd3.tar.bz2 yosys-f8f572fbfc4e5de3afa7dc05f5fa1feff87aabd3.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python_wrappers/globals_and_streams
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 28cd208cd..03985b1be 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -38,6 +38,17 @@ module IBUF( assign O = I; endmodule +module IBUFG( + output O, + (* iopad_external_pin *) + input I); + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + assign O = I; +endmodule + module OBUF( (* iopad_external_pin *) output O, |