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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-20 13:09:00 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-20 13:09:00 -0800 |
| commit | 1482f32d53da84ddfb034cff88174af5e5c41761 (patch) | |
| tree | 584578b1c793050b7c8ca93f5b7dcfd71dd3229d /techlibs/xilinx/cells_xtra.py | |
| parent | e58c3f8351763facc12f61c42797cc2a5edf0907 (diff) | |
| parent | 3b559de6e9f8972c1e52ee8bf6d9a600bcfa187f (diff) | |
| download | yosys-1482f32d53da84ddfb034cff88174af5e5c41761.tar.gz yosys-1482f32d53da84ddfb034cff88174af5e5c41761.tar.bz2 yosys-1482f32d53da84ddfb034cff88174af5e5c41761.zip | |
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
Interpret "abc9 -lut" as lut string only if [0-9:]
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
0 files changed, 0 insertions, 0 deletions