diff options
| author | David Shah <dave@ds0.me> | 2019-10-24 08:14:20 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-24 08:14:20 +0100 |
| commit | 34dadd9ab20494057c1ac7dae443b48eee0c2c30 (patch) | |
| tree | f413785a96c0b168e1275c44c6995067bc7f6d18 /techlibs/xilinx/cells_xtra.py | |
| parent | d49c6b2cba0256573352ae4dd5669e94ef75b60e (diff) | |
| parent | 3506eaf2904cddf5132c598a527e050a79a181d5 (diff) | |
| download | yosys-34dadd9ab20494057c1ac7dae443b48eee0c2c30.tar.gz yosys-34dadd9ab20494057c1ac7dae443b48eee0c2c30.tar.bz2 yosys-34dadd9ab20494057c1ac7dae443b48eee0c2c30.zip | |
Merge pull request #1455 from YosysHQ/dave/ultrascaleplus
Add BRAM and URAM mapping for UltraScale[+]
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 9a4747ff3..7cf1162bd 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -228,8 +228,8 @@ XC6V_CELLS = [ # Cell('FDSE'), Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}), Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - Cell('LDCE'), - Cell('LDPE'), + # Cell('LDCE'), + # Cell('LDPE'), Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}), # Slice/CLB primitives. @@ -378,8 +378,8 @@ XC7_CELLS = [ # Cell('FDSE'), Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}), Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - Cell('LDCE'), - Cell('LDPE'), + # Cell('LDCE'), + # Cell('LDPE'), Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}), # Slice/CLB primitives. @@ -435,8 +435,8 @@ XCU_CELLS = [ # Blockram. Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), + #Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), + #Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}), Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}), @@ -491,6 +491,12 @@ XCU_CELLS = [ Cell('PLLE3_BASE'), Cell('PLLE4_ADV'), Cell('PLLE4_BASE'), + # the "E2" variants are not strictly speaking UltraScale[+] cells + # but are automatically upgraded for backwards compatibility purposes + Cell('MMCME2_ADV'), + Cell('MMCME2_BASE'), + Cell('PLLE2_ADV'), + Cell('PLLE2_BASE'), # Configuration. Cell('BSCANE2', keep=True), @@ -562,8 +568,8 @@ XCU_CELLS = [ # Cell('FDSE'), Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}), Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - Cell('LDCE'), - Cell('LDPE'), + # Cell('LDCE'), + # Cell('LDPE'), Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}), # NOTE: not in the official library guide! |