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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-11-29 17:33:41 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-29 17:33:41 +0100 |
| commit | 5f4c35c7535f5a595d4e4f1adbd23b9bd594e205 (patch) | |
| tree | a059bf57adc0cdc261ed3b0d86b218cfa08087eb /techlibs/xilinx/cells_xtra.py | |
| parent | 419ca5c207087a1f39d8ec707ec1b94e3a481919 (diff) | |
| parent | 2badaa9adbf3fa976ac7e9d967e7d098de429bed (diff) | |
| download | yosys-5f4c35c7535f5a595d4e4f1adbd23b9bd594e205.tar.gz yosys-5f4c35c7535f5a595d4e4f1adbd23b9bd594e205.tar.bz2 yosys-5f4c35c7535f5a595d4e4f1adbd23b9bd594e205.zip | |
Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
xilinx: Add missing blackbox cell for BUFPLL.
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 82e403f78..01e7101d1 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -372,6 +372,7 @@ CELLS = [ Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFPLL', port_attrs={'IOCLK': ['clkbuf_driver']}), Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}), # Clock buffers (IO and regional) -- Virtex. |