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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 08:00:22 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-27 08:00:22 -0800 |
| commit | 6464dc35ec0c57b55aa19345b17eb34f47c15986 (patch) | |
| tree | 134e9c86e1b6ee1b276e6318e2f0d040a9890878 /techlibs/xilinx/cells_xtra.py | |
| parent | 41e0ddf4f4ac69b0c586b1c71e3ee200e1c892ce (diff) | |
| parent | de3476cc233c1c78d3e956aa7e9bd1003ac37f66 (diff) | |
| download | yosys-6464dc35ec0c57b55aa19345b17eb34f47c15986.tar.gz yosys-6464dc35ec0c57b55aa19345b17eb34f47c15986.tar.bz2 yosys-6464dc35ec0c57b55aa19345b17eb34f47c15986.zip | |
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
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