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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 10:32:51 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 11:31:12 -0800 |
| commit | 78d4fff69d09f46f1777213116f09826ba008991 (patch) | |
| tree | ea8424b1474f0967926feb637352f7026a69bae5 /techlibs/xilinx/cells_xtra.py | |
| parent | 968956badb977984133b00c38d0a08f3e2d0b854 (diff) | |
| download | yosys-78d4fff69d09f46f1777213116f09826ba008991.tar.gz yosys-78d4fff69d09f46f1777213116f09826ba008991.tar.bz2 yosys-78d4fff69d09f46f1777213116f09826ba008991.zip | |
xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
0 files changed, 0 insertions, 0 deletions