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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 23:39:14 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 23:39:14 -0800 |
| commit | 969f51141535ac70d8fbb2a0e2da7ee2aba833b8 (patch) | |
| tree | f1183177691e18d3ee5527aaa5fc8cce1baf6f59 /techlibs/xilinx/cells_xtra.py | |
| parent | 6318e3ce6df2484c4cc17856608e2a6354cd643a (diff) | |
| download | yosys-969f51141535ac70d8fbb2a0e2da7ee2aba833b8.tar.gz yosys-969f51141535ac70d8fbb2a0e2da7ee2aba833b8.tar.bz2 yosys-969f51141535ac70d8fbb2a0e2da7ee2aba833b8.zip | |
Promote output wires in sigmap so that can be detected
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
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