diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:53:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:53:20 -0700 |
| commit | a5ac33f230b5dd20273f6636e5b573ef0478b8f9 (patch) | |
| tree | 6f67a20084e1490fec10824cf4ff9eb4c6fe14e8 /techlibs/xilinx/cells_xtra.py | |
| parent | aae2b9fd9c8dc915fadacc24962436dd7aedff36 (diff) | |
| parent | 0acc51c3d82f65f73fa9e475c6fc41beabd925a6 (diff) | |
| download | yosys-a5ac33f230b5dd20273f6636e5b573ef0478b8f9.tar.gz yosys-a5ac33f230b5dd20273f6636e5b573ef0478b8f9.tar.bz2 yosys-a5ac33f230b5dd20273f6636e5b573ef0478b8f9.zip | |
Merge branch 'master' into eddie/abc_to_abc9
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 13dbc0e14..ee20ae992 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -137,7 +137,7 @@ XC6V_CELLS = [ Cell('SYSMON'), # Arithmetic functions. - Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), + #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Clock components. # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), @@ -264,7 +264,7 @@ XC7_CELLS = [ Cell('XADC'), # Arithmetic functions. - Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), + #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Clock components. # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), |