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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-28 12:57:36 -0800 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-28 12:57:36 -0800 |
| commit | b3a66dff7cac8ee98a9b26463e8858a38ea57f83 (patch) | |
| tree | b5e9335668fd02c912be638e806990345426b2fe /techlibs/xilinx/cells_xtra.py | |
| parent | 130d3b9639148fa8191937313a3ad21a7827df18 (diff) | |
| download | yosys-b3a66dff7cac8ee98a9b26463e8858a38ea57f83.tar.gz yosys-b3a66dff7cac8ee98a9b26463e8858a38ea57f83.tar.bz2 yosys-b3a66dff7cac8ee98a9b26463e8858a38ea57f83.zip | |
Move \init signal for non-port signals as long as internally driven
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
0 files changed, 0 insertions, 0 deletions