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| author | whitequark <whitequark@whitequark.org> | 2020-12-21 02:15:55 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-12-21 02:20:34 +0000 |
| commit | b9721bedf01ca1f536bbf13ba761333c6867bd29 (patch) | |
| tree | 5a262c642e0f07230fc81cc7a1a39344603a77a3 /techlibs/xilinx/cells_xtra.py | |
| parent | 40ca9d038b1e657b9b9ac17e7e5a2969c9922e00 (diff) | |
| download | yosys-b9721bedf01ca1f536bbf13ba761333c6867bd29.tar.gz yosys-b9721bedf01ca1f536bbf13ba761333c6867bd29.tar.bz2 yosys-b9721bedf01ca1f536bbf13ba761333c6867bd29.zip | |
cxxrtl: speed up bit repeats (sign extends, etc).
On Minerva SoC SRAM, depending on the compiler, this change improves
overall time by 4-7%.
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
0 files changed, 0 insertions, 0 deletions