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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:39:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 17:39:08 -0700 |
| commit | bbc0e06af3db4da924a3a92ced85adc87cf6abb6 (patch) | |
| tree | a96251669139f7026733d9583d766ce6b244a258 /techlibs/xilinx/cells_xtra.py | |
| parent | d4212d128b5985cf09f5e7f14bc06e7323e644ac (diff) | |
| parent | 0acc51c3d82f65f73fa9e475c6fc41beabd925a6 (diff) | |
| download | yosys-bbc0e06af3db4da924a3a92ced85adc87cf6abb6.tar.gz yosys-bbc0e06af3db4da924a3a92ced85adc87cf6abb6.tar.bz2 yosys-bbc0e06af3db4da924a3a92ced85adc87cf6abb6.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 13dbc0e14..ee20ae992 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -137,7 +137,7 @@ XC6V_CELLS = [ Cell('SYSMON'), # Arithmetic functions. - Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), + #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Clock components. # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), @@ -264,7 +264,7 @@ XC7_CELLS = [ Cell('XADC'), # Arithmetic functions. - Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), + #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Clock components. # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), |