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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-24 15:05:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-24 15:05:44 -0700 |
| commit | dc87372a97d515563ccccd517ef8f35662870fe6 (patch) | |
| tree | 9373bef80912453fd62497555dd97ab52f72d18e /techlibs/xilinx/cells_xtra.py | |
| parent | 10c41a5cf51427d96f465113decb752e501e926e (diff) | |
| download | yosys-dc87372a97d515563ccccd517ef8f35662870fe6.tar.gz yosys-dc87372a97d515563ccccd517ef8f35662870fe6.tar.bz2 yosys-dc87372a97d515563ccccd517ef8f35662870fe6.zip | |
Wire with init on FF part, 1'bx on non-FF part
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
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