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authorEddie Hung <eddie@fpgeh.com>2019-11-27 01:03:33 -0800
committerEddie Hung <eddie@fpgeh.com>2019-11-27 01:03:33 -0800
commitf6c0ec1d09c9bc065cc7266b299b41ebb59d6e26 (patch)
treec86d01623e4ac9ebeb91e61441812ddccc20fa07 /techlibs/xilinx/cells_xtra.py
parent4ba6f4f0d7c5754e04a0347a2b43a8640f7a6a35 (diff)
parent5e67df38edf5207a9b816946b094448cd6a52f88 (diff)
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Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
-rw-r--r--techlibs/xilinx/cells_xtra.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index f401ebe78..82e403f78 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -326,7 +326,7 @@ CELLS = [
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
# I/O.
- Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+ # Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}),
@@ -342,7 +342,7 @@ CELLS = [
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
# Output + tristate.
- Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+ # Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
# Pulls.
Cell('KEEPER'),