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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 10:59:03 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-28 10:59:03 -0700 |
| commit | da5f83039527bf50af001671744f351988c3261a (patch) | |
| tree | 5af77e4b5c61a5d31b18cc807818d884b6884ec1 /techlibs/xilinx/cells_xtra.sh | |
| parent | 74945dd738fca316f319771426646c4da327f662 (diff) | |
| parent | 38d8806bd74b9bb448c7488ec571e197fe2f96d6 (diff) | |
| download | yosys-da5f83039527bf50af001671744f351988c3261a.tar.gz yosys-da5f83039527bf50af001671744f351988c3261a.tar.bz2 yosys-da5f83039527bf50af001671744f351988c3261a.zip | |
Merge pull request #1098 from YosysHQ/xaig
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
Diffstat (limited to 'techlibs/xilinx/cells_xtra.sh')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh index 83863bf0b..53b528820 100644 --- a/techlibs/xilinx/cells_xtra.sh +++ b/techlibs/xilinx/cells_xtra.sh @@ -125,7 +125,7 @@ function xtract_cell_decl() xtract_cell_decl RAM32X1S_1 xtract_cell_decl RAM32X2S xtract_cell_decl RAM64M - xtract_cell_decl RAM64X1D + #xtract_cell_decl RAM64X1D xtract_cell_decl RAM64X1S xtract_cell_decl RAM64X1S_1 xtract_cell_decl RAM64X2S |