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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
| commit | 02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch) | |
| tree | af43bf9735fe47b09dbd8807c63fe451eb82aaba /techlibs/xilinx/cells_xtra.v | |
| parent | 3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff) | |
| parent | 61f37706f93042c2d1f093dd9bfa717390911eb3 (diff) | |
| download | yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.gz yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.bz2 yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.zip | |
Merge https://github.com/YosysHQ/yosys into read_aiger
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.v | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 8d8b91ddc..995d62e18 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -3695,6 +3695,25 @@ module RAM128X1S (...); input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE; endmodule +module RAM128X1D ( + output DPO, SPO, + input D, WCLK, WE, + input [6:0] A, DPRA +); + parameter [127:0] INIT = 128'bx; + parameter IS_WCLK_INVERTED = 0; +endmodule + +module RAM64X1D ( + output DPO, SPO, + input D, WCLK, WE, + input A0, A1, A2, A3, A4, A5, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 +); + parameter [63:0] INIT = 64'bx; + parameter IS_WCLK_INVERTED = 0; +endmodule + module RAM256X1S (...); parameter [255:0] INIT = 256'h0; parameter [0:0] IS_WCLK_INVERTED = 1'b0; |