diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 10:29:40 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-19 10:29:40 -0800 |
| commit | 94f15f023c8720d84211ac75980cf0b0f492411d (patch) | |
| tree | 29f40490883b15fec68ef6aba99767a0deaecc4f /techlibs/xilinx/cells_xtra.v | |
| parent | 76ba06a79ea917a0e515aa0e99ae41f42e8bddc9 (diff) | |
| parent | f52c6efd9da161e625538f9e8c23875efebda60f (diff) | |
| download | yosys-94f15f023c8720d84211ac75980cf0b0f492411d.tar.gz yosys-94f15f023c8720d84211ac75980cf0b0f492411d.tar.bz2 yosys-94f15f023c8720d84211ac75980cf0b0f492411d.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.v | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 8ac596459..66b7c583f 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -17,27 +17,6 @@ module FDCPE (...); input PRE; endmodule -module FDRSE (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; - output Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - (* invertible_pin = "IS_R_INVERTED" *) - input R; - (* invertible_pin = "IS_S_INVERTED" *) - input S; -endmodule - module LDCPE (...); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; |