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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-18 12:08:38 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-18 12:08:38 -0800 |
| commit | d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a (patch) | |
| tree | 526c60c70ac41f71eb0c1a0d83f556ce1b35b126 /techlibs/xilinx/cells_xtra.v | |
| parent | dccd7eb39f897f7fb04b038ee8ac11e676a8ea77 (diff) | |
| parent | 520f1646cf0c0d83603c4bec2f6a37acca1d4960 (diff) | |
| download | yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.tar.gz yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.tar.bz2 yosys-d0afe4e10d474e9254a6d5ebc7fbeeb8e2e0149a.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.v | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 8ac596459..66b7c583f 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -17,27 +17,6 @@ module FDCPE (...); input PRE; endmodule -module FDRSE (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_R_INVERTED = 1'b0; - parameter [0:0] IS_S_INVERTED = 1'b0; - output Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - (* invertible_pin = "IS_R_INVERTED" *) - input R; - (* invertible_pin = "IS_S_INVERTED" *) - input S; -endmodule - module LDCPE (...); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; |