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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 16:39:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 16:39:18 -0700 |
| commit | f1675b88f63b4c279e368d5ec9e6ca48f528024d (patch) | |
| tree | c2f436e5f9350b00d648a68b32bc693294f3ed26 /techlibs/xilinx/cells_xtra.v | |
| parent | c3df895bf464fd651c4d634ecb58ba78ca572f5f (diff) | |
| parent | efd04880dbeb2021c503c82ad962fe8c5d6802d4 (diff) | |
| download | yosys-f1675b88f63b4c279e368d5ec9e6ca48f528024d.tar.gz yosys-f1675b88f63b4c279e368d5ec9e6ca48f528024d.tar.bz2 yosys-f1675b88f63b4c279e368d5ec9e6ca48f528024d.zip | |
Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux
Diffstat (limited to 'techlibs/xilinx/cells_xtra.v')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.v | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 0ec3d0df0..15fa1b63a 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -3694,13 +3694,6 @@ module RAM32M (...); input WE; endmodule -module RAM32X1D (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO, SPO; - input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE; -endmodule - module RAM32X1S (...); parameter [31:0] INIT = 32'h00000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; |