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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-09 08:17:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-09 08:17:14 +0200 |
| commit | b00cad81d76bd83fe3210f8b84dec8c34acb7fd9 (patch) | |
| tree | 49aba5ace93677d5423d9a19a8acfc9e65f295ae /techlibs/xilinx/drams.txt | |
| parent | 21a1cc1b60f0c646dcc46c89440fc1a2cf606743 (diff) | |
| download | yosys-b00cad81d76bd83fe3210f8b84dec8c34acb7fd9.tar.gz yosys-b00cad81d76bd83fe3210f8b84dec8c34acb7fd9.tar.bz2 yosys-b00cad81d76bd83fe3210f8b84dec8c34acb7fd9.zip | |
Towards DRAM support in Xilinx flow
Diffstat (limited to 'techlibs/xilinx/drams.txt')
| -rw-r--r-- | techlibs/xilinx/drams.txt | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt new file mode 100644 index 000000000..84175b24c --- /dev/null +++ b/techlibs/xilinx/drams.txt @@ -0,0 +1,17 @@ + +bram $__XILINX_RAM32X1D + init 1 + abits 5 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +match $__XILINX_RAM32X1D +endmatch + |