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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 14:18:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 14:18:36 -0700 |
| commit | 569cd66764f43af9ea73038ce7437ab8557d497e (patch) | |
| tree | 6309ae90b08783f94e87e687f9688f94dc172358 /techlibs/xilinx/dsp_map.v | |
| parent | 9616dbd125171905bccf55fa7fd564e4ae2ca5ab (diff) | |
| parent | d38df68d26f1644539e5116e6b6c360e1c389cc9 (diff) | |
| download | yosys-569cd66764f43af9ea73038ce7437ab8557d497e.tar.gz yosys-569cd66764f43af9ea73038ce7437ab8557d497e.tar.bz2 yosys-569cd66764f43af9ea73038ce7437ab8557d497e.zip | |
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Diffstat (limited to 'techlibs/xilinx/dsp_map.v')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v index da1d6f3a9..2063c45e2 100644 --- a/techlibs/xilinx/dsp_map.v +++ b/techlibs/xilinx/dsp_map.v @@ -1,4 +1,4 @@ -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); +module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y); wire [47:0] P_48; DSP48E1 #( // Disable all registers @@ -20,8 +20,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); .PREG(0) ) _TECHMAP_REPLACE_ ( //Data path - .A({5'b0, A}), - .B(B), + .A({6'b0, A}), + .B({1'b0, B}), .C(48'b0), .D(24'b0), .P(P_48), |