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| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-10-08 17:00:30 +0000 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-10-22 18:06:57 +0200 |
| commit | 7b350cacd410b16fdac5a6933aea1bb009b83621 (patch) | |
| tree | 934e58717f9ba5463d97d56eaf8c82d875677494 /techlibs/xilinx/dsp_map.v | |
| parent | a3a7bb9bf7160d434db7a4737e68f6b015b221ef (diff) | |
| download | yosys-7b350cacd410b16fdac5a6933aea1bb009b83621.tar.gz yosys-7b350cacd410b16fdac5a6933aea1bb009b83621.tar.bz2 yosys-7b350cacd410b16fdac5a6933aea1bb009b83621.zip | |
xilinx: Support multiplier mapping for all families.
This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
Diffstat (limited to 'techlibs/xilinx/dsp_map.v')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 49 |
1 files changed, 0 insertions, 49 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v deleted file mode 100644 index a4256eb92..000000000 --- a/techlibs/xilinx/dsp_map.v +++ /dev/null @@ -1,49 +0,0 @@ -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 0; - parameter B_WIDTH = 0; - parameter Y_WIDTH = 0; - - wire [47:0] P_48; - DSP48E1 #( - // Disable all registers - .ACASCREG(0), - .ADREG(0), - .A_INPUT("DIRECT"), - .ALUMODEREG(0), - .AREG(0), - .BCASCREG(0), - .B_INPUT("DIRECT"), - .BREG(0), - .CARRYINREG(0), - .CARRYINSELREG(0), - .CREG(0), - .DREG(0), - .INMODEREG(0), - .MREG(0), - .OPMODEREG(0), - .PREG(0), - .USE_MULT("MULTIPLY"), - .USE_SIMD("ONE48"), - .USE_DPORT("FALSE") - ) _TECHMAP_REPLACE_ ( - //Data path - .A({{5{A[24]}}, A}), - .B(B), - .C(48'b0), - .D(25'b0), - .P(P_48), - - .INMODE(5'b00000), - .ALUMODE(4'b0000), - .OPMODE(7'b000101), - .CARRYINSEL(3'b000), - - .ACIN(30'b0), - .BCIN(18'b0), - .PCIN(48'b0), - .CARRYIN(1'b0) - ); - assign Y = P_48; -endmodule |