diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:00:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:00:03 -0700 |
| commit | b33ecd2a746b734fda33d8535afecf76bd35f59c (patch) | |
| tree | 42787f772fb84797029653456f652a395225f19f /techlibs/xilinx/dsp_map.v | |
| parent | cea7441d8ae7df8d22f510e6a101ec46a9d7751e (diff) | |
| download | yosys-b33ecd2a746b734fda33d8535afecf76bd35f59c.tar.gz yosys-b33ecd2a746b734fda33d8535afecf76bd35f59c.tar.bz2 yosys-b33ecd2a746b734fda33d8535afecf76bd35f59c.zip | |
Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little
Diffstat (limited to 'techlibs/xilinx/dsp_map.v')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v deleted file mode 100644 index 4faa204aa..000000000 --- a/techlibs/xilinx/dsp_map.v +++ /dev/null @@ -1,40 +0,0 @@ -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); - wire [47:0] P_48; - DSP48E1 #( - // Disable all registers - .ACASCREG(0), - .ADREG(0), - .A_INPUT("DIRECT"), - .ALUMODEREG(0), - .AREG(0), - .BCASCREG(0), - .B_INPUT("DIRECT"), - .BREG(0), - .CARRYINREG(0), - .CARRYINSELREG(0), - .CREG(0), - .DREG(0), - .INMODEREG(0), - .MREG(0), - .OPMODEREG(0), - .PREG(0) - ) _TECHMAP_REPLACE_ ( - //Data path - .A({5'b0, A}), - .B(B), - .C(48'b0), - .D(24'b0), - .P(P_48), - - .INMODE(4'b0000), - .ALUMODE(4'b0000), - .OPMODE(7'b000101), - .CARRYINSEL(3'b000), - - .ACIN(30'b0), - .BCIN(18'b0), - .PCIN(48'b0), - .CARRYIN(1'b0) - ); - assign OUT = P_48; -endmodule |