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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:09:34 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:09:34 +0100 |
| commit | 816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (patch) | |
| tree | 9be22cb0d132ebb6f7c361deb61bb7ebf67f1a8a /techlibs/xilinx/example_basys3/run_yosys.ys | |
| parent | 6978f3a77baa1220ba0f8a41ca26f5f7bc98dd0a (diff) | |
| download | yosys-816fe6bbe0ad90f7a696dd208dae6db8139dfd00.tar.gz yosys-816fe6bbe0ad90f7a696dd208dae6db8139dfd00.tar.bz2 yosys-816fe6bbe0ad90f7a696dd208dae6db8139dfd00.zip | |
Added Xilinx example for Basys3 board
Diffstat (limited to 'techlibs/xilinx/example_basys3/run_yosys.ys')
| -rw-r--r-- | techlibs/xilinx/example_basys3/run_yosys.ys | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/example_basys3/run_yosys.ys b/techlibs/xilinx/example_basys3/run_yosys.ys new file mode 100644 index 000000000..4541826d3 --- /dev/null +++ b/techlibs/xilinx/example_basys3/run_yosys.ys @@ -0,0 +1,2 @@ +read_verilog example.v +synth_xilinx -edif example.edif -top example |