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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-27 08:21:56 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-27 08:21:56 +0100 |
| commit | 02f321b6fcd17c94ad633d1070c03cbec1eb86e8 (patch) | |
| tree | e745314afedc87fe1fdbff2d2fa9121228afb404 /techlibs/xilinx/example_mojo_counter/example.sh | |
| parent | d9fa1e5a1d01e5a69dca6f8f0d760b047f29a772 (diff) | |
| download | yosys-02f321b6fcd17c94ad633d1070c03cbec1eb86e8.tar.gz yosys-02f321b6fcd17c94ad633d1070c03cbec1eb86e8.tar.bz2 yosys-02f321b6fcd17c94ad633d1070c03cbec1eb86e8.zip | |
Xilinx mojo_counter example is now working
Diffstat (limited to 'techlibs/xilinx/example_mojo_counter/example.sh')
| -rw-r--r-- | techlibs/xilinx/example_mojo_counter/example.sh | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/techlibs/xilinx/example_mojo_counter/example.sh b/techlibs/xilinx/example_mojo_counter/example.sh index 87af0ea31..466fadade 100644 --- a/techlibs/xilinx/example_mojo_counter/example.sh +++ b/techlibs/xilinx/example_mojo_counter/example.sh @@ -19,8 +19,12 @@ abc -lut 6; opt # map internal cells to FPGA cells techmap -map ../cells.v; opt +# insert clock buffers +select -set clocks */t:FDRE %x:+FDRE[C] */t:FDRE %d +iopadmap -inpad BUFGP O:I @clocks + # insert i/o buffers -iopadmap -outpad OBUF I:O -inpad BUFGP O:I +iopadmap -outpad OBUF I:O -inpad IBUF O:I @clocks %n # write netlist write_edif synth.edif |