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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-27 09:30:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-27 09:30:17 +0100 |
| commit | 90b016716b363977cf3dfc84d9502913469296ec (patch) | |
| tree | 0b0d669bc38f4e865600c31496117a19a6ca5e9c /techlibs/xilinx/example_sim_counter/counter.v | |
| parent | 02f321b6fcd17c94ad633d1070c03cbec1eb86e8 (diff) | |
| download | yosys-90b016716b363977cf3dfc84d9502913469296ec.tar.gz yosys-90b016716b363977cf3dfc84d9502913469296ec.tar.bz2 yosys-90b016716b363977cf3dfc84d9502913469296ec.zip | |
Moved simple xilinx counter sim example to subdir
Diffstat (limited to 'techlibs/xilinx/example_sim_counter/counter.v')
| -rw-r--r-- | techlibs/xilinx/example_sim_counter/counter.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/xilinx/example_sim_counter/counter.v b/techlibs/xilinx/example_sim_counter/counter.v new file mode 100644 index 000000000..72208bd80 --- /dev/null +++ b/techlibs/xilinx/example_sim_counter/counter.v @@ -0,0 +1,12 @@ +module counter (clk, rst, en, count); + + input clk, rst, en; + output reg [3:0] count; + + always @(posedge clk) + if (rst) + count <= 4'd0; + else if (en) + count <= count + 4'd1; + +endmodule |