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| author | Ahmed Irfan <irfan@levert.(none)> | 2015-04-03 16:38:07 +0200 |
|---|---|---|
| committer | Ahmed Irfan <irfan@levert.(none)> | 2015-04-03 16:38:07 +0200 |
| commit | bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee (patch) | |
| tree | 1d02541701054a1c3b1cdb66478d0cbc31c2d38f /techlibs/xilinx/example_sim_counter/run_sim.sh | |
| parent | 8acdd90bc918b780ad45cdac42b3baf84d2cc476 (diff) | |
| parent | 4b4490761949e738dee54bdfc52e080e0a5c9067 (diff) | |
| download | yosys-bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee.tar.gz yosys-bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee.tar.bz2 yosys-bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee.zip | |
Merge branch 'master' of https://github.com/cliffordwolf/yosys
Diffstat (limited to 'techlibs/xilinx/example_sim_counter/run_sim.sh')
| -rw-r--r-- | techlibs/xilinx/example_sim_counter/run_sim.sh | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh deleted file mode 100644 index b8354c002..000000000 --- a/techlibs/xilinx/example_sim_counter/run_sim.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -set -ex - -XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE - -../../../yosys -p 'synth_xilinx -top counter; write_verilog -noattr testbench_synth.v' counter.v - -iverilog -o testbench_gold counter_tb.v counter.v -iverilog -o testbench_gate counter_tb.v testbench_synth.v \ - $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6,BUFGP,IBUF}}.v - -./testbench_gold > testbench_gold.txt -./testbench_gate > testbench_gate.txt - -if diff -u testbench_gold.txt testbench_gate.txt; then - set +x; echo; echo; banner " PASS " -else - exit 1 -fi - -rm -f testbench_{synth,gold,gate,mapped}* - |