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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:10:46 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-01 17:10:46 +0100 |
| commit | 3cbfa3815ee0c40fcafe80d56afec97c36368f06 (patch) | |
| tree | 4f1ccade1714d31d8bb1443b4a1735a3174f0492 /techlibs/xilinx/example_sim_counter | |
| parent | 816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (diff) | |
| download | yosys-3cbfa3815ee0c40fcafe80d56afec97c36368f06.tar.gz yosys-3cbfa3815ee0c40fcafe80d56afec97c36368f06.tar.bz2 yosys-3cbfa3815ee0c40fcafe80d56afec97c36368f06.zip | |
Removed old XST-based xilinx examples
Diffstat (limited to 'techlibs/xilinx/example_sim_counter')
| -rw-r--r-- | techlibs/xilinx/example_sim_counter/counter.v | 12 | ||||
| -rw-r--r-- | techlibs/xilinx/example_sim_counter/counter_tb.v | 61 | ||||
| -rw-r--r-- | techlibs/xilinx/example_sim_counter/run_sim.sh | 23 |
3 files changed, 0 insertions, 96 deletions
diff --git a/techlibs/xilinx/example_sim_counter/counter.v b/techlibs/xilinx/example_sim_counter/counter.v deleted file mode 100644 index 72208bd80..000000000 --- a/techlibs/xilinx/example_sim_counter/counter.v +++ /dev/null @@ -1,12 +0,0 @@ -module counter (clk, rst, en, count); - - input clk, rst, en; - output reg [3:0] count; - - always @(posedge clk) - if (rst) - count <= 4'd0; - else if (en) - count <= count + 4'd1; - -endmodule diff --git a/techlibs/xilinx/example_sim_counter/counter_tb.v b/techlibs/xilinx/example_sim_counter/counter_tb.v deleted file mode 100644 index b6b64269e..000000000 --- a/techlibs/xilinx/example_sim_counter/counter_tb.v +++ /dev/null @@ -1,61 +0,0 @@ -`timescale 1 ns / 1 ps - -module testbench; - -reg clk, en, rst; -wire [3:0] count; - -counter uut_counter( - .clk(clk), - .count(count), - .en(en), - .rst(rst) -); - -initial begin - clk <= 0; - forever begin - #50; - clk <= ~clk; - end -end - -initial begin - @(posedge clk); - forever begin - @(posedge clk); - $display("%d", count); - end -end - -initial begin - rst <= 1; en <= 0; @(posedge clk); - rst <= 1; en <= 0; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 1; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 1; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - rst <= 0; en <= 1; @(posedge clk); - rst <= 0; en <= 0; @(posedge clk); - $finish; -end - -endmodule diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh deleted file mode 100644 index b8354c002..000000000 --- a/techlibs/xilinx/example_sim_counter/run_sim.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/bash - -set -ex - -XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE - -../../../yosys -p 'synth_xilinx -top counter; write_verilog -noattr testbench_synth.v' counter.v - -iverilog -o testbench_gold counter_tb.v counter.v -iverilog -o testbench_gate counter_tb.v testbench_synth.v \ - $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6,BUFGP,IBUF}}.v - -./testbench_gold > testbench_gold.txt -./testbench_gate > testbench_gate.txt - -if diff -u testbench_gold.txt testbench_gate.txt; then - set +x; echo; echo; banner " PASS " -else - exit 1 -fi - -rm -f testbench_{synth,gold,gate,mapped}* - |