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authorClifford Wolf <clifford@clifford.at>2013-11-24 17:47:22 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 17:47:22 +0100
commit41205afc39ae83881d82738765da148370eb5f4d (patch)
treede817a5331c36029a225f6b0f2db2e12926f9a25 /techlibs/xilinx/example_sim_counter
parent0ef22c76095bcca8ac7cacfc32e4ce6dd552addf (diff)
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Added proper dumping of signed/unsigned parameters to verilog backend
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