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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-27 14:35:15 -0700 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-27 14:35:15 -0700 |
| commit | 6bfeb17f05522b5f3e8839919b2d7aed85c7e2f0 (patch) | |
| tree | d3b3542d06ac5c5067c7cd73a0d75b486e4a50a9 /techlibs/xilinx/example_zed_counter/README | |
| parent | f39c0c992839fb79f667d404a6edc85bcb662dcf (diff) | |
| parent | 40b3551b45ea4a9901f68f1ecd0983270973a1f1 (diff) | |
| download | yosys-6bfeb17f05522b5f3e8839919b2d7aed85c7e2f0.tar.gz yosys-6bfeb17f05522b5f3e8839919b2d7aed85c7e2f0.tar.bz2 yosys-6bfeb17f05522b5f3e8839919b2d7aed85c7e2f0.zip | |
Merge pull request #12 from jameswalmsley/master
[EXAMPLES] Ported the mojo counter example to Zynq ZED board.
Diffstat (limited to 'techlibs/xilinx/example_zed_counter/README')
| -rw-r--r-- | techlibs/xilinx/example_zed_counter/README | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/techlibs/xilinx/example_zed_counter/README b/techlibs/xilinx/example_zed_counter/README new file mode 100644 index 000000000..539f24e73 --- /dev/null +++ b/techlibs/xilinx/example_zed_counter/README @@ -0,0 +1,10 @@ + +This is a simple example for Yosys synthesis targeting the ZED FPGA +development board [1, 2]. Simple script for xst-based synthesis (incl. +generation of reference edif files) and uploading to the board can be +found here [3]. + +[1] http://www.zedboard.org/ +[2] https://www.xilinx.com/zynq/ +[3] http://verilog.james.walms.co.uk/ + |