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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-31 18:11:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-31 18:11:46 -0700 |
| commit | 2228cef62f8550f85b203752681e2abeef1197ea (patch) | |
| tree | 77578bc790131eb6d7e6abc0a2a5f605e91de3c1 /techlibs/xilinx/ff_map.v | |
| parent | 01f71085f281d4721386018c90d3f95b2864df5b (diff) | |
| download | yosys-2228cef62f8550f85b203752681e2abeef1197ea.tar.gz yosys-2228cef62f8550f85b203752681e2abeef1197ea.tar.bz2 yosys-2228cef62f8550f85b203752681e2abeef1197ea.zip | |
Add flops as blackboxes
Diffstat (limited to 'techlibs/xilinx/ff_map.v')
| -rw-r--r-- | techlibs/xilinx/ff_map.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index 13beaa6ae..7c837814a 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -38,5 +38,12 @@ module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPL module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule +`ifndef DEPRECATED +module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule +module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule +module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule +module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule +`endif + `endif |