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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 12:28:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 12:28:46 -0700 |
| commit | 67f744d428b5385fbddc859c8e02f3e1ccfc17eb (patch) | |
| tree | 9b72bfe30f413f64064404b670bf38ab8d9e6f0d /techlibs/xilinx/ff_map.v | |
| parent | 2c18d530ea69094e7ed46dcf781d8f2517d4c61e (diff) | |
| download | yosys-67f744d428b5385fbddc859c8e02f3e1ccfc17eb.tar.gz yosys-67f744d428b5385fbddc859c8e02f3e1ccfc17eb.tar.bz2 yosys-67f744d428b5385fbddc859c8e02f3e1ccfc17eb.zip | |
Cleanup
Diffstat (limited to 'techlibs/xilinx/ff_map.v')
| -rw-r--r-- | techlibs/xilinx/ff_map.v | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index ce465130d..13beaa6ae 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -38,12 +38,5 @@ module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPL module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule -`ifndef DEPRECATED -module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule -module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule -module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule -module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule -`endif - `endif |