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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 09:46:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 09:46:35 -0700 |
| commit | a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91 (patch) | |
| tree | 49e471ade09346f2c17ebd00205e3dc70d1f7691 /techlibs/xilinx/ff_map.v | |
| parent | 6d74b3e004455a98d785bd27c4276b787af637a7 (diff) | |
| download | yosys-a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91.tar.gz yosys-a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91.tar.bz2 yosys-a76c8a7ffdfb879971c8c3d1b1f7e8392ddf2c91.zip | |
Fix initialisation of flops
Diffstat (limited to 'techlibs/xilinx/ff_map.v')
| -rw-r--r-- | techlibs/xilinx/ff_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index 8688c1c3b..1f0635614 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -28,7 +28,7 @@ module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); `else wire Q_next; - \$__ABC_FDRE #(/*.INIT(|0)*/) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0)); + \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0)); \$_FF_ abc_dff (.D(Q_next), .Q(Q)); `endif endmodule |