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| author | Marcin Kościelnicki <mwk@0x04.net> | 2020-02-03 18:37:28 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-02-07 09:03:22 +0100 |
| commit | 89adef352fde57fa599d66fe404c3c2b9e607a7f (patch) | |
| tree | 57dc27856458c388187570d43178f43f3503bb46 /techlibs/xilinx/lut4_lutrams.txt | |
| parent | d48950d92d748cc24ecfefc5beab19ea899982df (diff) | |
| download | yosys-89adef352fde57fa599d66fe404c3c2b9e607a7f.tar.gz yosys-89adef352fde57fa599d66fe404c3c2b9e607a7f.tar.bz2 yosys-89adef352fde57fa599d66fe404c3c2b9e607a7f.zip | |
xilinx: Add support for LUT RAM on LUT4-based devices.
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.
Fixes #1549
Diffstat (limited to 'techlibs/xilinx/lut4_lutrams.txt')
| -rw-r--r-- | techlibs/xilinx/lut4_lutrams.txt | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/techlibs/xilinx/lut4_lutrams.txt b/techlibs/xilinx/lut4_lutrams.txt new file mode 100644 index 000000000..2b344a9ee --- /dev/null +++ b/techlibs/xilinx/lut4_lutrams.txt @@ -0,0 +1,19 @@ +bram $__XILINX_RAM16X1D + init 1 + abits 4 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + + +match $__XILINX_RAM16X1D + min bits 2 + min wports 1 + make_outreg +endmatch |