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| author | gatecat <gatecat@ds0.me> | 2023-02-16 11:57:19 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-02-16 12:55:53 +0100 |
| commit | 25e7cb3bbb01d024b63cf8488cc3926f61e31804 (patch) | |
| tree | cab908b57938b7817d8781eb0718e7e8dc04b69c /techlibs/xilinx/lut_map.v | |
| parent | a20804c6ed0a734d13ddb43dda0f3ac976a62290 (diff) | |
| download | yosys-25e7cb3bbb01d024b63cf8488cc3926f61e31804.tar.gz yosys-25e7cb3bbb01d024b63cf8488cc3926f61e31804.tar.bz2 yosys-25e7cb3bbb01d024b63cf8488cc3926f61e31804.zip | |
fabulous: Add CLK to BRAM interface primitives
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'techlibs/xilinx/lut_map.v')
0 files changed, 0 insertions, 0 deletions