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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 12:55:26 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-20 12:55:26 -0700 |
| commit | 33960dd3d84b628f6e5de45c112368dc80626457 (patch) | |
| tree | 71f47cc0dce332fb4e3f15bedfde3327eb0ae60b /techlibs/xilinx/lutrams.txt | |
| parent | 14c03861b6d178c85d6963e673ed51bc142457e1 (diff) | |
| parent | d9fe4cccbf3cc03fa57b177fd13c6e900a2134f7 (diff) | |
| download | yosys-33960dd3d84b628f6e5de45c112368dc80626457.tar.gz yosys-33960dd3d84b628f6e5de45c112368dc80626457.tar.bz2 yosys-33960dd3d84b628f6e5de45c112368dc80626457.zip | |
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
[WIP] synth xilinx renaming, as per #1184
Diffstat (limited to 'techlibs/xilinx/lutrams.txt')
| -rw-r--r-- | techlibs/xilinx/lutrams.txt | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt new file mode 100644 index 000000000..2613c206c --- /dev/null +++ b/techlibs/xilinx/lutrams.txt @@ -0,0 +1,60 @@ + +bram $__XILINX_RAM32X1D + init 1 + abits 5 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X1D + init 1 + abits 6 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM128X1D + init 1 + abits 7 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +match $__XILINX_RAM32X1D + min bits 3 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64X1D + min bits 5 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM128X1D + min bits 9 + min wports 1 + make_outreg +endmatch + |