diff options
| author | N. Engelhardt <nak@symbioticeda.com> | 2020-01-03 12:28:48 +0100 |
|---|---|---|
| committer | N. Engelhardt <nak@symbioticeda.com> | 2020-01-03 12:28:48 +0100 |
| commit | 341fd872b59e8f95aa14afd9f17225d2c03a4283 (patch) | |
| tree | 21802e73ca767d124971d43d3f78d9f4cf7d62e2 /techlibs/xilinx/lutrams.txt | |
| parent | c8bc1793a4e8230c29fca4a34862414e8ab8722b (diff) | |
| parent | f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3 (diff) | |
| download | yosys-341fd872b59e8f95aa14afd9f17225d2c03a4283.tar.gz yosys-341fd872b59e8f95aa14afd9f17225d2c03a4283.tar.bz2 yosys-341fd872b59e8f95aa14afd9f17225d2c03a4283.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into abc_scratchpad_script
Diffstat (limited to 'techlibs/xilinx/lutrams.txt')
| -rw-r--r-- | techlibs/xilinx/lutrams.txt | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt index 2613c206c..29f6b05cc 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lutrams.txt @@ -1,4 +1,17 @@ +bram $__XILINX_RAM16X1D + init 1 + abits 4 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + bram $__XILINX_RAM32X1D init 1 abits 5 @@ -38,6 +51,70 @@ bram $__XILINX_RAM128X1D clkpol 0 2 endbram + +bram $__XILINX_RAM32X6SDP + init 1 + abits 5 + dbits 6 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X3SDP + init 1 + abits 6 + dbits 3 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM32X2Q + init 1 + abits 5 + dbits 2 + groups 2 + ports 3 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X1Q + init 1 + abits 6 + dbits 1 + groups 2 + ports 3 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + + +# Disabled for now, pending support for LUT4 arches +# since on LUT6 arches this occupies same area as +# a RAM32X1D +#match $__XILINX_RAM16X1D +# min bits 2 +# min wports 1 +# make_outreg +# or_next_if_better +#endmatch + match $__XILINX_RAM32X1D min bits 3 min wports 1 @@ -56,5 +133,35 @@ match $__XILINX_RAM128X1D min bits 9 min wports 1 make_outreg + or_next_if_better +endmatch + + +match $__XILINX_RAM32X6SDP + min bits 5 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64X3SDP + min bits 6 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM32X2Q + min bits 5 + min rports 3 + min wports 1 + make_outreg + or_next_if_better endmatch +match $__XILINX_RAM64X1Q + min bits 5 + min rports 3 + min wports 1 + make_outreg +endmatch |