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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 15:46:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-05 15:46:18 -0700 |
| commit | 0364a5d811f79364f35b72935fe90bc188229c19 (patch) | |
| tree | 221646765409f5eddcd066dc72b4bb17097fd008 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 544843da717734ab9bd9bd88f71db2475fc3abc0 (diff) | |
| parent | 97587015748eb9f7e0d55a1121f604b8b462b45a (diff) | |
| download | yosys-0364a5d811f79364f35b72935fe90bc188229c19.tar.gz yosys-0364a5d811f79364f35b72935fe90bc188229c19.tar.bz2 yosys-0364a5d811f79364f35b72935fe90bc188229c19.zip | |
Merge branch 'eddie/fix_retime' into xc7srl
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index cabf0b76e..ee8dec9ee 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -115,7 +115,7 @@ struct SynthXilinxPass : public Pass log(" opt -full\n"); log(" simplemap t:$dff t:$dffe (without -nosrl and without -retime only)\n"); log(" shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_cells:\n"); @@ -125,10 +125,10 @@ struct SynthXilinxPass : public Pass log(" clean\n"); log("\n"); log(" map_luts:\n"); - log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n"); - log(" abc -lut 5 [-dff] (with '-vpr' only!)\n"); + log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); + log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); - log(" techmap -map +/xilinx/lut_map.v\n"); + log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); log("\n"); log(" check:\n"); log(" hierarchy -check\n"); @@ -272,9 +272,9 @@ struct SynthXilinxPass : public Pass } if (vpr) { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); } else { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } Pass::call(design, "hierarchy -check"); @@ -291,9 +291,10 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); - Pass::call(design, "techmap -map +/xilinx/lut_map.v"); + Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); } if (check_label(active, run_from, run_to, "check")) |