diff options
| author | Marcin Kościelnicki <koriakin@0x04.net> | 2019-09-15 00:49:53 +0000 |
|---|---|---|
| committer | Marcin Kościelnicki <koriakin@0x04.net> | 2019-09-15 13:37:24 +0200 |
| commit | 09ac36da601aab607f01ccf6e2baa29296877877 (patch) | |
| tree | e9f58f58b5e8049fc7f86299335da949118e0f8c /techlibs/xilinx/synth_xilinx.cc | |
| parent | d9f99745da99c99111de358d92646cef2430fca7 (diff) | |
| download | yosys-09ac36da601aab607f01ccf6e2baa29296877877.tar.gz yosys-09ac36da601aab607f01ccf6e2baa29296877877.tar.bz2 yosys-09ac36da601aab607f01ccf6e2baa29296877877.zip | |
xilinx: Make blackbox library family-dependent.
Fixes #1246.
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e0e81ef1d..7467e024c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -46,7 +46,7 @@ struct SynthXilinxPass : public ScriptPass log(" -top <module>\n"); log(" use the specified module as top module\n"); log("\n"); - log(" -family {xcup|xcu|xc7|xc6s}\n"); + log(" -family {xcup|xcu|xc7|xc6v|xc6s}\n"); log(" run synthesis for the specified Xilinx architecture\n"); log(" generate the synthesis netlist for the specified family.\n"); log(" default: xc7\n"); @@ -244,7 +244,7 @@ struct SynthXilinxPass : public ScriptPass } extra_args(args, argidx, design); - if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s") + if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" & family != "xc6s") log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str()); if (widemux != 0 && widemux < 2) @@ -268,7 +268,7 @@ struct SynthXilinxPass : public ScriptPass { std::string ff_map_file; if (help_mode) - ff_map_file = "+/xilinx/xc6s_ff_map.v"; + ff_map_file = "+/xilinx/{family}_ff_map.v"; else if (family == "xc6s") ff_map_file = "+/xilinx/xc6s_ff_map.v"; else @@ -280,13 +280,22 @@ struct SynthXilinxPass : public ScriptPass else run("read_verilog -lib +/xilinx/cells_sim.v"); - run("read_verilog -lib +/xilinx/cells_xtra.v"); + if (help_mode) + run("read_verilog -lib +/xilinx/{family}_cells_xtra.v"); + else if (family == "xc6s") + run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v"); + else if (family == "xc6v") + run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v"); + else if (family == "xc7") + run("read_verilog -lib +/xilinx/xc7_cells_xtra.v"); + else if (family == "xcu" || family == "xcup") + run("read_verilog -lib +/xilinx/xcu_cells_xtra.v"); if (help_mode) { run("read_verilog -lib +/xilinx/{family}_brams_bb.v"); } else if (family == "xc6s") { run("read_verilog -lib +/xilinx/xc6s_brams_bb.v"); - } else if (family == "xc7") { + } else if (family == "xc6v" || family == "xc7") { run("read_verilog -lib +/xilinx/xc7_brams_bb.v"); } @@ -337,7 +346,7 @@ struct SynthXilinxPass : public ScriptPass if (family == "xc6s") { run("memory_bram -rules +/xilinx/xc6s_brams.txt"); run("techmap -map +/xilinx/xc6s_brams_map.v"); - } else if (family == "xc7") { + } else if (family == "xc6v" || family == "xc7") { run("memory_bram -rules +/xilinx/xc7_brams.txt"); run("techmap -map +/xilinx/xc7_brams_map.v"); } else { |