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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 08:10:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-14 08:10:02 -0700 |
| commit | 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75 (patch) | |
| tree | b9cc84592ebccaec275b5f3279f76297ef294e64 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 79b4a275ce85d231186105b6e73a596ff3326e1f (diff) | |
| download | yosys-26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.tar.gz yosys-26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.tar.bz2 yosys-26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.zip | |
Add shregmap -init_msb_first and use in synth_xilinx
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ce597ea4a..71b468e38 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -105,7 +105,7 @@ struct SynthXilinxPass : public Pass log(" dff2dffe\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); - log(" shregmap -init -params -enpol any_or_none\n"); + log(" shregmap -init_msb_first -params -enpol any_or_none\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); @@ -225,7 +225,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); - Pass::call(design, "shregmap -init -params -enpol any_or_none"); + Pass::call(design, "shregmap -init_msb_first -params -enpol any_or_none"); Pass::call(design, "opt -fast"); } |