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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-12 17:54:07 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-12 23:41:27 +0200 |
| commit | 347dd01c2f7dff6e8222c5f9d360f84a17c937b5 (patch) | |
| tree | 2ce79cc1ddda483a78510e7cfe717dc14bbd62ab /techlibs/xilinx/synth_xilinx.cc | |
| parent | b33744b03ab8c8188e45656722d4a28c173ec67c (diff) | |
| download | yosys-347dd01c2f7dff6e8222c5f9d360f84a17c937b5.tar.gz yosys-347dd01c2f7dff6e8222c5f9d360f84a17c937b5.tar.bz2 yosys-347dd01c2f7dff6e8222c5f9d360f84a17c937b5.zip | |
xilinx: Fix srl regression.
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9. Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index de0de5974..421602e62 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -652,13 +652,13 @@ struct SynthXilinxPass : public ScriptPass } run("clean"); + if (help_mode || !abc9) + run("techmap -map +/xilinx/ff_map.v", "(only if not '-abc9')"); // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming if (!nosrl || help_mode) run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')"); std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"; - if (help_mode || !abc9) - techmap_args += stringf(" -map +/xilinx/ff_map.v"); techmap_args += " -D LUT_WIDTH=" + lut_size_s; run("techmap " + techmap_args); if (help_mode) |