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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:19:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:19:52 -0700 |
| commit | 4883391b6331e62226c46e797f82a31ef9ef81a3 (patch) | |
| tree | 3779d9d3c226602b96eb6f72e2c780e02c64df3e /techlibs/xilinx/synth_xilinx.cc | |
| parent | d06d4f35c376672ad1042b46bb29d7bd2bfa5243 (diff) | |
| parent | bc98a463a433e5b1553b307301e67e641a148d3c (diff) | |
| download | yosys-4883391b6331e62226c46e797f82a31ef9ef81a3.tar.gz yosys-4883391b6331e62226c46e797f82a31ef9ef81a3.tar.bz2 yosys-4883391b6331e62226c46e797f82a31ef9ef81a3.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 8a531c497..08d74cd3b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -116,14 +116,15 @@ struct SynthXilinxPass : public Pass log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); log("\n"); + log(" map_cells:\n"); + log(" techmap -map +/xilinx/cells_map.v\n"); + log(" clean\n"); + log("\n"); log(" map_luts:\n"); log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n"); log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); - log("\n"); - log(" map_cells:\n"); - log(" techmap -map +/xilinx/cells_map.v\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); log(" clean\n"); @@ -274,17 +275,18 @@ struct SynthXilinxPass : public Pass Pass::call(design, "opt -fast"); } + if (check_label(active, run_from, run_to, "map_cells")) + { + Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + Pass::call(design, "clean"); + } + if (check_label(active, run_from, run_to, "map_luts")) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?"); Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); - } - - if (check_label(active, run_from, run_to, "map_cells")) - { - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); Pass::call(design, "clean"); |