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author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-05-21 12:47:55 -0700 |
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committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-05-21 12:47:55 -0700 |
commit | 489c555b41330ed9b1d69afdd8f44ef1e9a9be59 (patch) | |
tree | 64bdc5903bf099d59aa9ba9dacff03d8b7a9eda2 /techlibs/xilinx/synth_xilinx.cc | |
parent | 509f729e55458eda0ed7869ad269ec52d1956043 (diff) | |
parent | c907899422884d959632ed42c6589a0720b681e4 (diff) | |
download | yosys-489c555b41330ed9b1d69afdd8f44ef1e9a9be59.tar.gz yosys-489c555b41330ed9b1d69afdd8f44ef1e9a9be59.tar.bz2 yosys-489c555b41330ed9b1d69afdd8f44ef1e9a9be59.zip |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 8aa7b508e..c20cac09b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -42,6 +42,10 @@ struct SynthXilinxPass : public ScriptPass log(" -top <module>\n"); log(" use the specified module as top module\n"); log("\n"); + log(" -arch {xcup|xcu|xc7|xc6s}\n"); + log(" run synthesis for the specified Xilinx architecture\n"); + log(" default: xc7\n"); + log("\n"); log(" -edif <file>\n"); log(" write the design to the specified edif file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); @@ -80,7 +84,7 @@ struct SynthXilinxPass : public ScriptPass log("\n"); } - std::string top_opt, edif_file, blif_file; + std::string top_opt, edif_file, blif_file, arch; bool flatten, retime, vpr, nobram, nodram, nosrl; void clear_flags() YS_OVERRIDE @@ -94,6 +98,7 @@ struct SynthXilinxPass : public ScriptPass nobram = false; nodram = false; nosrl = false; + arch = "xc7"; } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -108,6 +113,10 @@ struct SynthXilinxPass : public ScriptPass top_opt = "-top " + args[++argidx]; continue; } + if (args[argidx] == "-arch" && argidx+1 < args.size()) { + arch = args[++argidx]; + continue; + } if (args[argidx] == "-edif" && argidx+1 < args.size()) { edif_file = args[++argidx]; continue; @@ -152,6 +161,9 @@ struct SynthXilinxPass : public ScriptPass } extra_args(args, argidx, design); + if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s") + log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str()); + if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); @@ -257,7 +269,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("check")) { run("hierarchy -check"); - run("stat"); + run("stat -tech xilinx"); run("check -noinit"); } |