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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-01 10:53:23 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-01 10:53:23 -0800 |
| commit | 66fd6396d4795ea9559cbbd1560387e7d7e79596 (patch) | |
| tree | eec885cceb81e9cb57d62ad5b8333f0b6f4f56b6 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 60e3c38054f10251021fa2f504ad2424da33aa1d (diff) | |
| parent | ca2b3feed82f923f06d0cf57787818f0f6793157 (diff) | |
| download | yosys-66fd6396d4795ea9559cbbd1560387e7d7e79596.tar.gz yosys-66fd6396d4795ea9559cbbd1560387e7d7e79596.tar.bz2 yosys-66fd6396d4795ea9559cbbd1560387e7d7e79596.zip | |
Merge pull request #841 from mmicko/master
Fix ECP5 cells_sim for iverilog
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
0 files changed, 0 insertions, 0 deletions