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| author | David Shah <dave@ds0.me> | 2019-10-18 13:24:19 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-10-23 11:47:37 +0100 |
| commit | 6769d31ddbab341940af9b42b538fca60797fdf4 (patch) | |
| tree | a80cd15e8fdd3d4cf58ea30a7596c5d6a2a8b64b /techlibs/xilinx/synth_xilinx.cc | |
| parent | f02623abb5d8338f034d7069844418af8912ab0f (diff) | |
| download | yosys-6769d31ddbab341940af9b42b538fca60797fdf4.tar.gz yosys-6769d31ddbab341940af9b42b538fca60797fdf4.tar.bz2 yosys-6769d31ddbab341940af9b42b538fca60797fdf4.zip | |
xilinx: Add support for UltraScale[+] BRAM mapping
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6566da832..825addf84 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -305,6 +305,8 @@ struct SynthXilinxPass : public ScriptPass run("read_verilog -lib +/xilinx/xc6s_brams_bb.v"); } else if (family == "xc6v" || family == "xc7") { run("read_verilog -lib +/xilinx/xc7_brams_bb.v"); + } else if (family == "xcu" || family == "xcup") { + run("read_verilog -lib +/xilinx/xcu_brams_bb.v"); } run(stringf("hierarchy -check %s", top_opt.c_str())); @@ -417,8 +419,11 @@ struct SynthXilinxPass : public ScriptPass run("memory_bram -rules +/xilinx/xc6s_brams.txt"); run("techmap -map +/xilinx/xc6s_brams_map.v"); } else if (family == "xc6v" || family == "xc7") { - run("memory_bram -rules +/xilinx/xc7_brams.txt"); + run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt"); run("techmap -map +/xilinx/xc7_brams_map.v"); + } else if (family == "xcu" || family == "xcup") { + run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt"); + run("techmap -map +/xilinx/xcu_brams_map.v"); } else { log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str()); } |