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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 10:21:05 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 10:21:05 -0800 |
| commit | 68f38f2ee0e82ac7250e8c4b257e33fd62d21544 (patch) | |
| tree | f645c4053dfb8095b8b74d2f9736b072bdb434d6 /techlibs/xilinx/synth_xilinx.cc | |
| parent | c9ab18889a63f74534c6fe9184ccb32e3661ab90 (diff) | |
| download | yosys-68f38f2ee0e82ac7250e8c4b257e33fd62d21544.tar.gz yosys-68f38f2ee0e82ac7250e8c4b257e33fd62d21544.tar.bz2 yosys-68f38f2ee0e82ac7250e8c4b257e33fd62d21544.zip | |
synth_xilinx to use shregmap with -params too
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index afd868743..4e4139154 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -223,7 +223,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - Pass::call(design, "shregmap -init"); + Pass::call(design, "shregmap -init -params"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); Pass::call(design, "opt -fast"); |