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| author | Clifford Wolf <clifford@clifford.at> | 2018-03-07 17:31:07 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-03-07 17:31:48 +0100 |
| commit | 6991c132b501ebb48fa5dd1b0f995bb544261556 (patch) | |
| tree | 5b43209f73172cb8412ee7831dc42a7da9c78f4d /techlibs/xilinx/synth_xilinx.cc | |
| parent | 73c01dca6540e389393c0ec606fd3c9c4b6d95c4 (diff) | |
| download | yosys-6991c132b501ebb48fa5dd1b0f995bb544261556.tar.gz yosys-6991c132b501ebb48fa5dd1b0f995bb544261556.tar.bz2 yosys-6991c132b501ebb48fa5dd1b0f995bb544261556.zip | |
Add Xilinx RAM64X1D and RAM128X1D simulation models
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e7ec1e6e8..b60295ac0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -71,7 +71,6 @@ struct SynthXilinxPass : public Pass { log(" read_verilog -lib +/xilinx/cells_sim.v\n"); log(" read_verilog -lib +/xilinx/cells_xtra.v\n"); log(" read_verilog -lib +/xilinx/brams_bb.v\n"); - log(" read_verilog -lib +/xilinx/drams_bb.v\n"); log(" hierarchy -check -top <top>\n"); log("\n"); log(" flatten: (only if -flatten)\n"); @@ -168,7 +167,6 @@ struct SynthXilinxPass : public Pass { Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v"); Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v"); Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v"); - Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v"); Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str())); } |