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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-17 15:39:54 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-17 15:39:54 +0100 |
| commit | 703123114530e6010b854b5e3a5a1c0a153fa4b6 (patch) | |
| tree | cfbd59ab90b17659a080fe17bea82e416699ebc9 /techlibs/xilinx/synth_xilinx.cc | |
| parent | a95c229e12496194b513e3623ab44f9530f272ba (diff) | |
| download | yosys-703123114530e6010b854b5e3a5a1c0a153fa4b6.tar.gz yosys-703123114530e6010b854b5e3a5a1c0a153fa4b6.tar.bz2 yosys-703123114530e6010b854b5e3a5a1c0a153fa4b6.zip | |
Added MUXCY and XORCY support to synth_xilinx
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 289de4399..35bc4302e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -73,7 +73,11 @@ struct SynthXilinxPass : public Pass { log(" techmap -map +/xilinx/brams.v\n"); log("\n"); log(" fine:\n"); - log(" synth -run fine\n"); + log(" opt -fast -full\n"); + log(" memory_map\n"); + log(" opt -full\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith.v\n"); + log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); log(" abc -lut 6:8\n"); @@ -144,7 +148,11 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "fine")) { - Pass::call(design, "synth -run fine"); + Pass::call(design, "opt -fast -full"); + Pass::call(design, "memory_map"); + Pass::call(design, "opt -full"); + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith.v"); + Pass::call(design, "opt -fast"); } if (check_label(active, run_from, run_to, "map_luts")) |