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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-28 23:48:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-28 23:48:17 -0700 |
| commit | 79b6edb6397c530a7304eb4334f95324a4208aba (patch) | |
| tree | 3a3c3fd9511c2dbe31e0fcbf71771596eeb6a2c3 /techlibs/xilinx/synth_xilinx.cc | |
| parent | cfa6dd61ef79fb16abd83164b1e013c0a5a2a63a (diff) | |
| download | yosys-79b6edb6397c530a7304eb4334f95324a4208aba.tar.gz yosys-79b6edb6397c530a7304eb4334f95324a4208aba.tar.bz2 yosys-79b6edb6397c530a7304eb4334f95324a4208aba.zip | |
Big rework; flop info now mostly in cells_sim.v
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 888b5ed7b..f5143ca82 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -276,9 +276,9 @@ struct SynthXilinxPass : public ScriptPass if (check_label("begin")) { if (vpr) - run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); + run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); else - run("read_verilog -lib +/xilinx/cells_sim.v"); + run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v"); if (help_mode) run("read_verilog -lib +/xilinx/{family}_cells_xtra.v"); |