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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 09:56:30 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 8408c13405bfe561e6a6022e2730ecca18a1464a (patch) | |
| tree | a0c005bce8422388a7a8b1517ff8baf4778256e2 /techlibs/xilinx/synth_xilinx.cc | |
| parent | ac24a23e31f2da76f8b976cd89b9ec6fadf15374 (diff) | |
| download | yosys-8408c13405bfe561e6a6022e2730ecca18a1464a.tar.gz yosys-8408c13405bfe561e6a6022e2730ecca18a1464a.tar.bz2 yosys-8408c13405bfe561e6a6022e2730ecca18a1464a.zip | |
Update xilinx for ABC9
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index bb3ced8da..8553efd6b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -619,7 +619,7 @@ struct SynthXilinxPass : public ScriptPass if (dff_mode) techmap_args += " -D DFF_MODE"; run("techmap " + techmap_args); - run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v"); + run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v"); std::string abc9_opts; auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str()); if (active_design->scratchpad.count(k)) |